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Figure 5 from A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery | Semantic Scholar
Energy Efficient High-Speed Links Electrical and Optical Interconnect Architectures to Enable Tera-Scale Computing
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Figure 2 from Challenges in the design of high-speed clock and data recovery circuits | Semantic Scholar
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Clock and Data Recovery/Structures and types of CDRs/The CDR phase comparator - Wikibooks, open books for an open world
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Modified Hogge detector implementation to achieve low phase offset and... | Download Scientific Diagram
Energy Efficient High-Speed Links Electrical and Optical Interconnect Architectures to Enable Tera-Scale Computing
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